newlib fix is pending: riscv: configure.ac bug fix for misaligned access when __riscv_misaligned_slow
Thanks!
I can try and see if I can make a minimal example that recreates the race condition but I’ll be OOO this week so maybe next
The problem is related to
Problem is that RISC-V standard ABI requires unaligned support but on PolarFire it is guaranteed for unprivileged user and supervisor modes by machine level firmware misaligned access emulation in SBI (usually OpenSBI). But RTEMS runs in the machine mode and does not want to allow latency and visibility uncontrolled SBI code use/run. The code of NewLib, RTEMS and all other components and programs should be build with GCC option -mstrict-align. There can be some problem in third party low-level code if it expects misaligned loads over generated and computed pointers works. So such sequences enabled when RISC-V target is detected, specified by some defines, should be located and witched to behavior for MIPS or other architectures which do not allows misaligned abscesses. Other option is to include misaligned accesses emulation directly in RTEMS M-mode exception handler. But such approach lowers determinism and control over maximal letency.