/dts-v1/;

/ {
 compatible = "ti,am33xx";
 #address-cells = <1>;
 #size-cells = <1>;
 cpu0_opp_table: opp-table {
  compatible = "operating-points-v2-ti-cpu";
  syscon = <&scm_conf>;
  opp-50-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <950000 931000 969000>;
   opp-supported-hw = <0x06 0x0010>;
   opp-suspend;
  };
  opp-100-275000000 {
   opp-hz = /bits/ 64 <275000000>;
   opp-microvolt = <1100000 1078000 1122000>;
   opp-supported-hw = <0x01 0x00FF>;
   opp-suspend;
  };
  opp-100-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <1100000 1078000 1122000>;
   opp-supported-hw = <0x06 0x0020>;
   opp-suspend;
  };
  opp-100-500000000 {
   opp-hz = /bits/ 64 <500000000>;
   opp-microvolt = <1100000 1078000 1122000>;
   opp-supported-hw = <0x01 0xFFFF>;
  };
  opp-100-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <1100000 1078000 1122000>;
   opp-supported-hw = <0x06 0x0040>;
  };
  opp-120-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <1200000 1176000 1224000>;
   opp-supported-hw = <0x01 0xFFFF>;
  };
  opp-120-720000000 {
   opp-hz = /bits/ 64 <720000000>;
   opp-microvolt = <1200000 1176000 1224000>;
   opp-supported-hw = <0x06 0x0080>;
  };
  opp-720000000 {
   opp-hz = /bits/ 64 <720000000>;
   opp-microvolt = <1260000 1234800 1285200>;
   opp-supported-hw = <0x01 0xFFFF>;
  };
  opp-800000000 {
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <1260000 1234800 1285200>;
   opp-supported-hw = <0x06 0x0100>;
  };
  opp-1000000000 {
   opp-hz = /bits/ 64 <1000000000>;
   opp-microvolt = <1325000 1298500 1351500>;
   opp-supported-hw = <0x04 0x0200>;
  };
 };
};


/ {
 model = "TI AM335x BeagleBone Black";
 compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
 interrupt-parent = <&intc>;
 l4_wkup: target-module@44c00000 {
   status = "okay";
 };
 l4_fast: target-module@4a000000 {
   status = "okay";
 };
};

&cpu0_opp_table {
 opp-1000000000 {
  opp-supported-hw = <0x06 0x0100>;
 };
};

&l4_wkup {
 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus", "simple-bus";
 clock-names = "fck";
 reg = <0x44c00000 0x800>,
       <0x44c00800 0x800>,
       <0x44c01000 0x400>,
       <0x44c01400 0x400>;
 reg-names = "ap", "la", "ia0", "ia1";
 #address-cells = <1>;
 #size-cells = <1>;
 ranges = <0x00000000 0x44c00000 0x100000>,
          <0x00100000 0x44d00000 0x100000>,
          <0x00200000 0x44e00000 0x100000>;
 intc: interrupt-controller@48200000 {
  compatible = "ti,am33xx-intc";
  interrupt-controller;
  #interrupt-cells = <1>;
  reg = <0x48200000 0x1000>;
 };
 segment@0 {
  compatible = "simple-pm-bus", "simple-bus";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x00000000 0x00000000 0x000800>,
           <0x00000800 0x00000800 0x000800>,
           <0x00001000 0x00001000 0x000400>,
           <0x00001400 0x00001400 0x000400>;
 };
 segment@200000 {
  compatible = "simple-pm-bus", "simple-bus";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x00000000 0x00200000 0x002000>,
           <0x00002000 0x00202000 0x001000>,
           <0x00003000 0x00203000 0x001000>,
           <0x00004000 0x00204000 0x001000>,
           <0x00005000 0x00205000 0x001000>,
           <0x00006000 0x00206000 0x001000>,
           <0x00007000 0x00207000 0x001000>,
           <0x00008000 0x00208000 0x001000>,
           <0x00009000 0x00209000 0x001000>,
           <0x0000a000 0x0020a000 0x001000>,
           <0x0000b000 0x0020b000 0x001000>,
           <0x0000c000 0x0020c000 0x001000>,
           <0x0000d000 0x0020d000 0x001000>,
           <0x0000f000 0x0020f000 0x001000>,
           <0x00010000 0x00210000 0x010000>,
           <0x00020000 0x00220000 0x010000>,
           <0x00030000 0x00230000 0x001000>,
           <0x00031000 0x00231000 0x001000>,
           <0x00032000 0x00232000 0x001000>,
           <0x00033000 0x00233000 0x001000>,
           <0x00034000 0x00234000 0x001000>,
           <0x00035000 0x00235000 0x001000>,
           <0x00036000 0x00236000 0x001000>,
           <0x00037000 0x00237000 0x001000>,
           <0x00038000 0x00238000 0x001000>,
           <0x00039000 0x00239000 0x001000>,
           <0x0003a000 0x0023a000 0x001000>,
           <0x0003e000 0x0023e000 0x001000>,
           <0x0003f000 0x0023f000 0x001000>,
           <0x0000e000 0x0020e000 0x001000>,
           <0x00040000 0x00240000 0x040000>,
           <0x00080000 0x00280000 0x001000>;
  target-module@0 {
   compatible = "ti,sysc-omap4", "ti,sysc";
   reg = <0 0x4>;
   reg-names = "rev";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x0 0x2000>;
   prcm: prcm@0 {
    compatible = "ti,am3-prcm", "simple-bus";
    reg = <0 0x2000>;
    #address-cells = <1>;
    #size-cells = <1>;
    ranges = <0 0 0x2000>;
    prcm_clocks: clocks {
     #address-cells = <1>;
     #size-cells = <0>;
    };
    prcm_clockdomains: clockdomains {
    };
   };
  };
  target-module@10000 {
   compatible = "ti,sysc-omap4", "ti,sysc";
   reg = <0x10000 0x4>;
   reg-names = "rev";
   clock-names = "fck";
   ti,no-idle;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x00000000 0x00010000 0x00010000>,
            <0x00010000 0x00020000 0x00010000>;
   scm@0 {
    compatible = "ti,am3-scm", "simple-bus";
    reg = <0x0 0x2000>;
    #address-cells = <1>;
    #size-cells = <1>;
    #pinctrl-cells = <1>;
    ranges = <0 0 0x2000>;
    scm_conf: scm_conf@0 {
     compatible = "syscon", "simple-bus";
     reg = <0x0 0x800>;
     #address-cells = <1>;
     #size-cells = <1>;
     ranges = <0 0 0x800>;
     phy_gmii_sel: phy-gmii-sel {
      compatible = "ti,am3352-phy-gmii-sel";
      reg = <0x650 0x4>;
      #phy-cells = <2>;
     };
     scm_clocks: clocks {
      #address-cells = <1>;
      #size-cells = <0>;
     };
    };
   };
  };
 };
};

&l4_fast {
 compatible = "ti,sysc-omap4-simple", "ti,sysc";
 clocks = <&l4hs_clkctrl ((0x120) - 0x120) 0>;
 clock-names = "fck";
 reg = <0x4a000000 0x800>,
       <0x4a000800 0x800>,
       <0x4a001000 0x400>;
 reg-names = "ap", "la", "ia0";
 #address-cells = <1>;
 #size-cells = <1>;
 ranges = <0x00000000 0x4a000000 0x1000000>;
 target-module@100000 {
  compatible = "ti,sysc-omap4-simple", "ti,sysc";
  reg = <0x101200 0x4>,
        <0x101208 0x4>,
        <0x101204 0x4>;
  reg-names = "rev", "sysc", "syss";
  ti,sysc-mask = <0>;
  ti,sysc-midle = <0>,
    <1>;
  ti,sysc-sidle = <0>,
    <1>;
  ti,syss-mask = <1>;
  clocks = <&cpsw_125mhz_clkctrl ((0x14) - 0x0) 0>;
  clock-names = "fck";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x0 0x100000 0x8000>;
  ethernet@0 {
   compatible = "ti,am335x-cpsw","ti,cpsw";
   clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
   clock-names = "fck", "cpts";
   cpdma_channels = <8>;
   ale_entries = <1024>;
   bd_ram_size = <0x2000>;
   mac_control = <0x20>;
   slaves = <2>;
   active_slave = <0>;
   cpts_clock_mult = <0x80000000>;
   cpts_clock_shift = <29>;
   reg = <0x0 0x800
          0x1200 0x100>;
   #address-cells = <1>;
   #size-cells = <1>;
   interrupts = <40>, <41>, <42>, <43>;
   ranges = <0 0 0x8000>;
   syscon = <&scm_conf>;
   status = "okay";
   mdio@1000 {
    compatible = "ti,cpsw-mdio","ti,davinci_mdio";
    clocks = <&cpsw_125mhz_clkctrl ((0x14) - 0x0) 0>;
    clock-names = "fck";
    #address-cells = <1>;
    #size-cells = <0>;
    bus_freq = <1000000>;
    reg = <0x1000 0x100>;
    status = "okay";
   };
   slave@200 {
    phy_id = <&davinci_mdio>, <0>;
    phy-mode = "rgmii-txid";
    mac-address = [ 00 00 00 00 00 00 ];
    phys = <&phy_gmii_sel 1 1>;
   };
   slave@300 {
    phy_id = <&davinci_mdio>, <1>;
    phy-mode = "rgmii-txid";
    mac-address = [ 00 00 00 00 00 00 ];
    phys = <&phy_gmii_sel 2 1>;
   };
  };
  switch@0 {
   compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch";
   reg = <0x0 0x4000>;
   ranges = <0 0 0x4000>;
   clocks = <&cpsw_125mhz_gclk>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   syscon = <&scm_conf>;
   status = "okay";
   interrupts = <40>, <41>, <42>, <43>;
   interrupt-names = "rx_thresh", "rx", "tx", "misc";
   ethernet-ports {
    #address-cells = <1>;
    #size-cells = <0>;
    port@1 {
     reg = <1>;
     label = "port1";
     mac-address = [ 00 00 00 00 00 00 ];
     phys = <&phy_gmii_sel 1 1>;
    };
    port@2 {
     reg = <2>;
     label = "port2";
     mac-address = [ 00 00 00 00 00 00 ];
     phys = <&phy_gmii_sel 2 1>;
    };
   };
   davinci_mdio: mdio@1000 {
    compatible = "ti,cpsw-mdio","ti,davinci_mdio";
    clocks = <&cpsw_125mhz_gclk>;
    clock-names = "fck";
    #address-cells = <1>;
    #size-cells = <0>;
    bus_freq = <1000000>;
    reg = <0x1000 0x100>;
   };
   cpts {
    clocks = <&cpsw_cpts_rft_clk>;
    clock-names = "cpts";
   };
  };
 };
 target-module@180000 {
  compatible = "ti,sysc";
  status = "disabled";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x0 0x180000 0x20000>;
 };
 target-module@200000 {
  compatible = "ti,sysc";
  status = "disabled";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x0 0x200000 0x80000>;
 };
 pruss_tm: target-module@300000 {
  compatible = "ti,sysc-pruss", "ti,sysc";
  reg = <0x326000 0x4>,
        <0x326004 0x4>;
  reg-names = "rev", "sysc";
  ti,sysc-mask = <((1 << 4) |
     (1 << 5))>;
  ti,sysc-midle = <0>,
    <1>,
    <2>;
  ti,sysc-sidle = <0>,
    <1>,
    <2>;
  clocks = <&pruss_ocp_clkctrl ((0xe8) - 0xe8) 0>;
  clock-names = "fck";
  resets = <&prm_per 1>;
  reset-names = "rstctrl";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x0 0x300000 0x80000>;
  status = "disabled";
  pruss: pruss@0 {
   compatible = "ti,am3356-pruss";
   reg = <0x0 0x80000>;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;
   pruss_mem: memories@0 {
    reg = <0x0 0x2000>,
          <0x2000 0x2000>,
          <0x10000 0x3000>;
    reg-names = "dram0", "dram1",
         "shrdram2";
   };
   pruss_cfg: cfg@26000 {
    compatible = "ti,pruss-cfg", "syscon";
    reg = <0x26000 0x2000>;
    #address-cells = <1>;
    #size-cells = <1>;
    ranges = <0x0 0x26000 0x2000>;
    clocks {
     #address-cells = <1>;
     #size-cells = <0>;
     pruss_iepclk_mux: iepclk-mux@30 {
      reg = <0x30>;
      #clock-cells = <0>;
      clocks = <&l3_gclk>,
        <&pruss_ocp_gclk>;
     };
    };
   };
   pruss_mii_rt: mii-rt@32000 {
    compatible = "ti,pruss-mii", "syscon";
    reg = <0x32000 0x58>;
   };
   pruss_intc: interrupt-controller@20000 {
    compatible = "ti,pruss-intc";
    reg = <0x20000 0x2000>;
    interrupts = <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>;
    interrupt-names = "host_intr0", "host_intr1",
        "host_intr2", "host_intr3",
        "host_intr4", "host_intr5",
        "host_intr6", "host_intr7";
    interrupt-controller;
    #interrupt-cells = <3>;
   };
   pru0: pru@34000 {
    compatible = "ti,am3356-pru";
    reg = <0x34000 0x2000>,
          <0x22000 0x400>,
          <0x22400 0x100>;
    reg-names = "iram", "control", "debug";
    firmware-name = "am335x-pru0-fw";
   };
   pru1: pru@38000 {
    compatible = "ti,am3356-pru";
    reg = <0x38000 0x2000>,
          <0x24000 0x400>,
          <0x24400 0x100>;
    reg-names = "iram", "control", "debug";
    firmware-name = "am335x-pru1-fw";
   };
   pruss_mdio: mdio@32400 {
    compatible = "ti,davinci_mdio";
    reg = <0x32400 0x90>;
    clocks = <&dpll_core_m4_ck>;
    clock-names = "fck";
    bus_freq = <1000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };
  };
 };
};

&prcm {
 prm_per: prm@c00 {
  compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  reg = <0xc00 0x100>;
  #reset-cells = <1>;
  #power-domain-cells = <0>;
 };
 prm_wkup: prm@d00 {
  compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  reg = <0xd00 0x100>;
  #reset-cells = <1>;
  #power-domain-cells = <0>;
 };
 prm_mpu: prm@e00 {
  compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  reg = <0xe00 0x100>;
  #power-domain-cells = <0>;
 };
 prm_device: prm@f00 {
  compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  reg = <0xf00 0x100>;
  #reset-cells = <1>;
 };
 prm_rtc: prm@1000 {
  compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  reg = <0x1000 0x100>;
  #power-domain-cells = <0>;
 };
 prm_gfx: prm@1100 {
  compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  reg = <0x1100 0x100>;
  #power-domain-cells = <0>;
  #reset-cells = <1>;
 };
 prm_cefuse: prm@1200 {
  compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
  reg = <0x1200 0x100>;
  #power-domain-cells = <0>;
 };
};

&scm_clocks {
 sys_clkin_ck: clock-sys-clkin-22@40 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "sys_clkin_ck";
  clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
  ti,bit-shift = <22>;
  reg = <0x0040>;
 };
 adc_tsc_fck: clock-adc-tsc-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "adc_tsc_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 dcan0_fck: clock-dcan0-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "dcan0_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 dcan1_fck: clock-dcan1-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "dcan1_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 mcasp0_fck: clock-mcasp0-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "mcasp0_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 mcasp1_fck: clock-mcasp1-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "mcasp1_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 smartreflex0_fck: clock-smartreflex0-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "smartreflex0_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 smartreflex1_fck: clock-smartreflex1-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "smartreflex1_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 sha0_fck: clock-sha0-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "sha0_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 aes0_fck: clock-aes0-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "aes0_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 rng_fck: clock-rng-fck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "rng_fck";
  clocks = <&sys_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 clock@664 {
  compatible = "ti,clksel";
  reg = <0x664>;
  #clock-cells = <2>;
  #address-cells = <1>;
  #size-cells = <0>;
  ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 {
   reg = <0>;
   #clock-cells = <0>;
   compatible = "ti,gate-clock";
   clock-output-names = "ehrpwm0_tbclk";
   clocks = <&l4ls_gclk>;
  };
  ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 {
   reg = <1>;
   #clock-cells = <0>;
   compatible = "ti,gate-clock";
   clock-output-names = "ehrpwm1_tbclk";
   clocks = <&l4ls_gclk>;
  };
  ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 {
   reg = <2>;
   #clock-cells = <0>;
   compatible = "ti,gate-clock";
   clock-output-names = "ehrpwm2_tbclk";
   clocks = <&l4ls_gclk>;
  };
 };
};

&prcm_clocks {
 clk_32768_ck: clock-clk-32768 {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-output-names = "clk_32768_ck";
  clock-frequency = <32768>;
 };
 clk_rc32k_ck: clock-clk-rc32k {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-output-names = "clk_rc32k_ck";
  clock-frequency = <32000>;
 };
 virt_19200000_ck: clock-virt-19200000 {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-output-names = "virt_19200000_ck";
  clock-frequency = <19200000>;
 };
 virt_24000000_ck: clock-virt-24000000 {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-output-names = "virt_24000000_ck";
  clock-frequency = <24000000>;
 };
 virt_25000000_ck: clock-virt-25000000 {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-output-names = "virt_25000000_ck";
  clock-frequency = <25000000>;
 };
 virt_26000000_ck: clock-virt-26000000 {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-output-names = "virt_26000000_ck";
  clock-frequency = <26000000>;
 };
 tclkin_ck: clock-tclkin {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-output-names = "tclkin_ck";
  clock-frequency = <12000000>;
 };
 dpll_core_ck: clock@490 {
  #clock-cells = <0>;
  compatible = "ti,am3-dpll-core-clock";
  clock-output-names = "dpll_core_ck";
  clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
  reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
 };
 dpll_core_x2_ck: clock-dpll-core-x2 {
  #clock-cells = <0>;
  compatible = "ti,am3-dpll-x2-clock";
  clock-output-names = "dpll_core_x2_ck";
  clocks = <&dpll_core_ck>;
 };
 dpll_core_m4_ck: clock-dpll-core-m4@480 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clock-output-names = "dpll_core_m4_ck";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <31>;
  reg = <0x0480>;
  ti,index-starts-at-one;
 };
 dpll_core_m5_ck: clock-dpll-core-m5@484 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clock-output-names = "dpll_core_m5_ck";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <31>;
  reg = <0x0484>;
  ti,index-starts-at-one;
 };
 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clock-output-names = "dpll_core_m6_ck";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <31>;
  reg = <0x04d8>;
  ti,index-starts-at-one;
 };
 dpll_mpu_ck: clock@488 {
  #clock-cells = <0>;
  compatible = "ti,am3-dpll-clock";
  clock-output-names = "dpll_mpu_ck";
  clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
  reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
 };
 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clock-output-names = "dpll_mpu_m2_ck";
  clocks = <&dpll_mpu_ck>;
  ti,max-div = <31>;
  reg = <0x04a8>;
  ti,index-starts-at-one;
 };
 dpll_ddr_ck: clock@494 {
  #clock-cells = <0>;
  compatible = "ti,am3-dpll-no-gate-clock";
  clock-output-names = "dpll_ddr_ck";
  clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
  reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
 };
 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clock-output-names = "dpll_ddr_m2_ck";
  clocks = <&dpll_ddr_ck>;
  ti,max-div = <31>;
  reg = <0x04a0>;
  ti,index-starts-at-one;
 };
 dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "dpll_ddr_m2_div2_ck";
  clocks = <&dpll_ddr_m2_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };
 dpll_disp_ck: clock@498 {
  #clock-cells = <0>;
  compatible = "ti,am3-dpll-no-gate-clock";
  clock-output-names = "dpll_disp_ck";
  clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
  reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
 };
 dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clock-output-names = "dpll_disp_m2_ck";
  clocks = <&dpll_disp_ck>;
  ti,max-div = <31>;
  reg = <0x04a4>;
  ti,index-starts-at-one;
  ti,set-rate-parent;
 };
 dpll_per_ck: clock@48c {
  #clock-cells = <0>;
  compatible = "ti,am3-dpll-no-gate-j-type-clock";
  clock-output-names = "dpll_per_ck";
  clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
  reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
 };
 dpll_per_m2_ck: clock-dpll-per-m2@4ac {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clock-output-names = "dpll_per_m2_ck";
  clocks = <&dpll_per_ck>;
  ti,max-div = <31>;
  reg = <0x04ac>;
  ti,index-starts-at-one;
 };
 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
  clocks = <&dpll_per_m2_ck>;
  clock-mult = <1>;
  clock-div = <4>;
 };
 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "dpll_per_m2_div4_ck";
  clocks = <&dpll_per_m2_ck>;
  clock-mult = <1>;
  clock-div = <4>;
 };
 clk_24mhz: clock-clk-24mhz {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "clk_24mhz";
  clocks = <&dpll_per_m2_ck>;
  clock-mult = <1>;
  clock-div = <8>;
 };
 clkdiv32k_ck: clock-clkdiv32k {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "clkdiv32k_ck";
  clocks = <&clk_24mhz>;
  clock-mult = <1>;
  clock-div = <732>;
 };
 l3_gclk: clock-l3-gclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "l3_gclk";
  clocks = <&dpll_core_m4_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "pruss_ocp_gclk";
  clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
  reg = <0x0530>;
 };
 mmu_fck: clock-mmu-fck-1@914 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clock-output-names = "mmu_fck";
  clocks = <&dpll_core_m4_ck>;
  ti,bit-shift = <1>;
  reg = <0x0914>;
 };
 timer1_fck: clock-timer1-fck@528 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "timer1_fck";
  clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
  reg = <0x0528>;
 };
 timer2_fck: clock-timer2-fck@508 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "timer2_fck";
  clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>;
  reg = <0x0508>;
 };
 timer3_fck: clock-timer3-fck@50c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "timer3_fck";
  clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>;
  reg = <0x050c>;
 };
 timer4_fck: clock-timer4-fck@510 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "timer4_fck";
  clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>;
  reg = <0x0510>;
 };
 timer5_fck: clock-timer5-fck@518 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "timer5_fck";
  clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>;
  reg = <0x0518>;
 };
 timer6_fck: clock-timer6-fck@51c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "timer6_fck";
  clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>;
  reg = <0x051c>;
 };
 timer7_fck: clock-timer7-fck@504 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "timer7_fck";
  clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>;
  reg = <0x0504>;
 };
 usbotg_fck: clock-usbotg-fck-8@47c {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clock-output-names = "usbotg_fck";
  clocks = <&dpll_per_ck>;
  ti,bit-shift = <8>;
  reg = <0x047c>;
 };
 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "dpll_core_m4_div2_ck";
  clocks = <&dpll_core_m4_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };
 ieee5000_fck: clock-ieee5000-fck-1@e4 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clock-output-names = "ieee5000_fck";
  clocks = <&dpll_core_m4_div2_ck>;
  ti,bit-shift = <1>;
  reg = <0x00e4>;
 };
 wdt1_fck: clock-wdt1-fck@538 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "wdt1_fck";
  clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>;
  reg = <0x0538>;
 };
 l4_rtc_gclk: clock-l4-rtc-gclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "l4_rtc_gclk";
  clocks = <&dpll_core_m4_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };
 l4hs_gclk: clock-l4hs-gclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "l4hs_gclk";
  clocks = <&dpll_core_m4_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 l3s_gclk: clock-l3s-gclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "l3s_gclk";
  clocks = <&dpll_core_m4_div2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 l4fw_gclk: clock-l4fw-gclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "l4fw_gclk";
  clocks = <&dpll_core_m4_div2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 l4ls_gclk: clock-l4ls-gclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "l4ls_gclk";
  clocks = <&dpll_core_m4_div2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 sysclk_div_ck: clock-sysclk-div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "sysclk_div_ck";
  clocks = <&dpll_core_m4_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };
 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "cpsw_125mhz_gclk";
  clocks = <&dpll_core_m5_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };
 cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "cpsw_cpts_rft_clk";
  clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
  reg = <0x0520>;
 };
 gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "gpio0_dbclk_mux_ck";
  clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl ((0x14c) - 0x14c) 0>;
  reg = <0x053c>;
 };
 lcd_gclk: clock-lcd-gclk@534 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clock-output-names = "lcd_gclk";
  clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
  reg = <0x0534>;
  ti,set-rate-parent;
 };
 mmc_clk: clock-mmc {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clock-output-names = "mmc_clk";
  clocks = <&dpll_per_m2_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };
 clock@52c {
  compatible = "ti,clksel";
  reg = <0x52c>;
  #clock-cells = <2>;
  #address-cells = <1>;
  #size-cells = <0>;
  gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {
   reg = <1>;
   #clock-cells = <0>;
   compatible = "ti,mux-clock";
   clock-output-names = "gfx_fclk_clksel_ck";
   clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
  };
  gfx_fck_div_ck: clock-gfx-fck-div@0 {
   reg = <0>;
   #clock-cells = <0>;
   compatible = "ti,divider-clock";
   clock-output-names = "gfx_fck_div_ck";
   clocks = <&gfx_fclk_clksel_ck>;
   ti,max-div = <2>;
  };
 };
 clock@700 {
  compatible = "ti,clksel";
  reg = <0x700>;
  #clock-cells = <2>;
  #address-cells = <1>;
  #size-cells = <0>;
  sysclkout_pre_ck: clock-sysclkout-pre@0 {
   reg = <0>;
   #clock-cells = <0>;
   compatible = "ti,mux-clock";
   clock-output-names = "sysclkout_pre_ck";
   clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
  };
  clkout2_div_ck: clock-clkout2-div@3 {
   reg = <3>;
   #clock-cells = <0>;
   compatible = "ti,divider-clock";
   clock-output-names = "clkout2_div_ck";
   clocks = <&sysclkout_pre_ck>;
   ti,max-div = <8>;
  };
  clkout2_ck: clock-clkout2@7 {
   reg = <7>;
   #clock-cells = <0>;
   compatible = "ti,gate-clock";
   clock-output-names = "clkout2_ck";
   clocks = <&clkout2_div_ck>;
  };
 };
};

&prcm {
 per_cm: clock@0 {
  compatible = "ti,omap4-cm";
  clock-output-names = "per_cm";
  reg = <0x0 0x400>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x0 0x400>;
  l4ls_clkctrl: clock@38 {
   compatible = "ti,clkctrl";
   clock-output-names = "l4ls_clkctrl";
   reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
   #clock-cells = <2>;
  };
  l3s_clkctrl: clock@1c {
   compatible = "ti,clkctrl";
   clock-output-names = "l3s_clkctrl";
   reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
   #clock-cells = <2>;
  };
  l3_clkctrl: clock@24 {
   compatible = "ti,clkctrl";
   clock-output-names = "l3_clkctrl";
   reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
   #clock-cells = <2>;
  };
  l4hs_clkctrl: clock@120 {
   compatible = "ti,clkctrl";
   clock-output-names = "l4hs_clkctrl";
   reg = <0x120 0x4>;
   #clock-cells = <2>;
  };
  pruss_ocp_clkctrl: clock@e8 {
   compatible = "ti,clkctrl";
   clock-output-names = "pruss_ocp_clkctrl";
   reg = <0xe8 0x4>;
   #clock-cells = <2>;
  };
  cpsw_125mhz_clkctrl: clock@0 {
   compatible = "ti,clkctrl";
   clock-output-names = "cpsw_125mhz_clkctrl";
   reg = <0x0 0x18>;
   #clock-cells = <2>;
  };
  lcdc_clkctrl: clock@18 {
   compatible = "ti,clkctrl";
   clock-output-names = "lcdc_clkctrl";
   reg = <0x18 0x4>;
   #clock-cells = <2>;
  };
  clk_24mhz_clkctrl: clock@14c {
   compatible = "ti,clkctrl";
   clock-output-names = "clk_24mhz_clkctrl";
   reg = <0x14c 0x4>;
   #clock-cells = <2>;
  };
 };
 wkup_cm: clock@400 {
  compatible = "ti,omap4-cm";
  clock-output-names = "wkup_cm";
  reg = <0x400 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x400 0x100>;
  l4_wkup_clkctrl: clock@0 {
   compatible = "ti,clkctrl";
   clock-output-names = "l4_wkup_clkctrl";
   reg = <0x0 0x10>, <0xb4 0x24>;
   #clock-cells = <2>;
  };
  l3_aon_clkctrl: clock@14 {
   compatible = "ti,clkctrl";
   clock-output-names = "l3_aon_clkctrl";
   reg = <0x14 0x4>;
   #clock-cells = <2>;
  };
  l4_wkup_aon_clkctrl: clock@b0 {
   compatible = "ti,clkctrl";
   clock-output-names = "l4_wkup_aon_clkctrl";
   reg = <0xb0 0x4>;
   #clock-cells = <2>;
  };
 };
 mpu_cm: clock@600 {
  compatible = "ti,omap4-cm";
  clock-output-names = "mpu_cm";
  reg = <0x600 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x600 0x100>;
  mpu_clkctrl: clock@0 {
   compatible = "ti,clkctrl";
   clock-output-names = "mpu_clkctrl";
   reg = <0x0 0x8>;
   #clock-cells = <2>;
  };
 };
 l4_rtc_cm: clock@800 {
  compatible = "ti,omap4-cm";
  clock-output-names = "l4_rtc_cm";
  reg = <0x800 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x800 0x100>;
  l4_rtc_clkctrl: clock@0 {
   compatible = "ti,clkctrl";
   clock-output-names = "l4_rtc_clkctrl";
   reg = <0x0 0x4>;
   #clock-cells = <2>;
  };
 };
 gfx_l3_cm: clock@900 {
  compatible = "ti,omap4-cm";
  clock-output-names = "gfx_l3_cm";
  reg = <0x900 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x900 0x100>;
  gfx_l3_clkctrl: clock@0 {
   compatible = "ti,clkctrl";
   clock-output-names = "gfx_l3_clkctrl";
   reg = <0x0 0x8>;
   #clock-cells = <2>;
  };
 };
 l4_cefuse_cm: clock@a00 {
  compatible = "ti,omap4-cm";
  clock-output-names = "l4_cefuse_cm";
  reg = <0xa00 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0xa00 0x100>;
  l4_cefuse_clkctrl: clock@0 {
   compatible = "ti,clkctrl";
   clock-output-names = "l4_cefuse_clkctrl";
   reg = <0x0 0x24>;
   #clock-cells = <2>;
  };
 };
};

/ {
 freebsd,dts-version = "7.1";
};