In cpukit/include/rtems/error.h at line 100. There was a #if 0 deactivated code.
It was for defining error codes for specific errors. Right now the error codes are hard coded for 32 bit.
The main task was to generalise the logic for defining the errors so the error codes are computed with respect to architecture of board or cpu (16, 32, 64 , etc). This part is done.
But to verify whether the logic is fine I had problem regarding testing the logic on various architecture boards.
I had followed the GSOC guidelines for initialising the environment with the source-builder and rtems repository. and have also built sparc/erc32 BSP.
I was having problems with testing the system on the board and also downloading other relevant BSP.
I ran the 64 bit and 32 bit RISC-V targets with qemu simulation.
[riscv/rv64imafdc]
[riscv/rv32imafdc]
The Aarch targets wern’t compiling the tests for some reason with or without my changes.
I had written custom tests to verify my changes in the hello test. Do you wish for me to create another test so one can verify it later?
I did the MR
the static assert is ensuring whether the error bits are greater than 8 or not and returning assertion whether the size of rtems_error_code_t is small or large.
This is used as self explanation so we dont need any new tests for verifying the error codes.
ok, I think it makes sense to add a test case also, because there is a requirement being imposed here (that RTEMS_ERROR_ERRNO is the highest order bit).
