GSoC 2026: Introduction and Proof of Work - Yasssine (RP2350 BSP)

[yassine-cherni]

Hi,

I’m Yassine, Microelectronics & Embedded System student at ISIMM.
I noticed issue #5536 still has no proposal, so here I am. I have completed the Getting Started guide built the erc32 BSP, modified the Hello World sample and ran it in the simulator. Screenshot and patch attached.

0001-hello-Add-custom-greeting-for-GSoC-2026-demonstratio.txt (777 Bytes)
I would prefer to start with the RISC-V Hazard3 core since RISC-V is
an open ISA which aligns well with the open source spirit of RTEMS,
then complete the ARM Cortex-M33 side once the RISC-V port is stable.

Looking forward to any feedback from @opticron.

[gedare]

Hi Yassine, you can add yourself to tracking/2026 · main · RTEMS / Programs / Google Summer of Code · GitLab and search here for topics related to your project interests or start a new topic if no current topics about it. That said, it is probably too late for you to put together a competitive GSoC proposal in this round.

[amar]

Hello, do you have an RP2350 board on hand to show us that you can run something on it? Doesn’t matter what it is. Thank you.

[yassine-cherni]

Hi @amar, thanks for reaching out! Yes, I do have an RP2350 board and I’m ready to move forward.

[amar]

That’s great, please send us a screenshot of you running something on it.

[yassine-cherni]

Hi @amar,
My approach uses two RP2350 boards ( RPI Pico 2 ): one configured as a Debugprobe (CMSIS-DAP) and the other as the target device. The Debugprobe is detected over USB, and I can communicate with the target using picotool and OpenOCD.

I’ve attached a screenshot of the terminal output and a photo of my physical setup.

Best regards,
Yassine

[amar]

This is great, thanks.