Introduction
Hello everyone,
I am Dhruva P V (aka Dhrulian). I am currently pursuing my 4th year of Engineering in Electronics and Communication. With a strong passion for Embedded Systems, I’m always looking forward to learning, collaborating, and exploring new technologies. I found the RTEMS GSoC program to be the perfect opportunity to achieve all of these goals.
Mandatory Task Completion
I have successfully completed the mandatory task:
- Architecture: SPARC
- BSP: erc32
Patch:
My Contributions to RTEMS
Through these contributions, I have learned RTEMS workflow and development standards:
-
Score: Added checks to handle cases where the node was off_chain .
MR: !871 -
Documentation: Added unsupported_methods in the posix-users directory .
MR: !200
GSoC 2026 Focus
With the current GSoC 2026 focus, I am interested in working on:
“RISC-V in Supervisor Mode” - #3337
I have created a separate post for this and will update it with the required initial tasks, my research, and reasoning.
I would appreciate any suggestions or guidance from the maintainers and community members on this.
Thank you.